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| LTC4099 1 4099f n media players n portable navigation devices n smart phones n industrial handhelds n portable medical instruments n switching regulator with bat-track tm adaptive output control makes optimal use of limited input power n i 2 c port for optimal system performance and status information n input overvoltage protection n bat-track control of external step-down switching regulator maximizes ef? ciency from automotive and other high voltage sources n instant-on operation with low battery n optional overtemperature battery conditioner improves high temperature battery safety margin n ideal diode seamlessly connects battery when input power is limited or unavailable n full-featured li-ion/polymer battery charger n 1.5a maximum charge current with thermal limiting n slew control reduces switching emi n ultra-thin (0.55mm) 20-lead 3mm 4mm qfn typical application features applications description i 2 c controlled usb power manager/charger with overvoltage protection the ltc ? 4099 is an i 2 c controlled high ef? ciency usb powerpath? controller and full-featured li-ion/polymer battery charger. it seamlessly manages power distribution from multiple sources including usb, a wall adapter and a li-ion/polymer battery. the LTC4099 automatically limits its input current for usb compatibility. for automotive and other high volt- age applications, the LTC4099 interfaces with an external switching regulator. both the usb input and the auxiliary input controller feature bat-track optimized charging to provide maximum power to the application and reduced heat in high power density applications. the i 2 c port allows digital control of important application parameters including input current limit, charge current and ? oat voltage. several status bits can also be read back via i 2 c. an overvoltage protection circuit guards the LTC4099 from high voltage damage on the low voltage v bus pin. the LTC4099 is available in the ultra-thin (0.55mm) 20-lead 3mm 4mm qfn surface mount package. i 2 c controlled high ef? ciency battery charger/ usb power manager reduced power dissipation vs linear battery charger v bus usb overvoltage protection 10f 10f 0.1f 3.01k 1.02k 6.2k to controller system load 4099 ta01a clprog prog LTC4099 gnd sw 3.3h ntc ovsens i 2 c ovgate v out bat batsens ntcbias 2 li-ion 100k 100k t + , lt, ltc and ltm are registered trademarks of linear technology corporation. powerpath and bat-track are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 6522118, 6570372, 6700364, 6819094. other patents pending. linear battery charger switching battery charger battery voltage (v) 3.3 power dissipation (w) 1.2 1.4 1.6 4 1.0 0.8 3.5 3.7 3.4 3.6 3.8 3.9 4.1 0.2 0 0.6 1.8 0.4 4099 ta01b v in = 5v i charge = 1a additional power available for charging
LTC4099 2 4099f absolute maximum ratings electrical characteristics v bus , wall (transient) t < 1ms, duty cycle < 1% ...................................... C0.3v to 7v v bus , wall (static), bat, batsens, irq , ntc, dv cc ............................................... C0.3v to 6v sda, scl .......... C0.3v to max (v bus , v out , bat) + 0.3v i ovsens .................................................................10ma i clprog ....................................................................3ma i prog , i ntcbias .........................................................2ma i out , i sw , i bat , i vbus ...................................................2a maximum junction temperature........................... 125c operating temperature range.................. C40c to 85c storage temperature range ................... C65c to 125c i irq .........................................................................50ma i acpr ......................................................................5ma (notes 1, 2, 3) the l denotes the speci? cations which apply over the full operating temp- erature range, otherwise speci? cations are at t a = 25c. v bus = 5v, bat = 3.8v, dv cc = 3.3v, r prog = 1.02k, r clprog = 3.01k, unless otherwise noted. symbol parameter conditions min typ max units input power supply v bus input supply voltage l 4.35 5.5 v i bus(lim) total input current 100ma mode 500ma mode 620ma mode 790ma mode 1a mode 1.2a mode low power suspend mode high power suspend mode l l l l 88 460 580 725 920 1150 0.30 1.6 93 485 620 790 965 1220 0.37 2.05 100 500 650 850 1000 1295 0.5 2.5 ma ma ma ma ma ma ma ma i vbusq (note 4) input quiescent current 100ma mode 500ma, 620ma, 790ma, 1a, 1.2a modes low power suspend mode high power suspend mode 6 15 0.039 0.037 ma ma ma ma pin configuration 20 19 18 17 7 8 top view 21 pdc package 20-lead (3mm s 4mm) plastic utqfn 9 10 6 5 4 3 2 1 11 12 13 14 15 16 ovgate ntc ntcbias v c wall batsens scl dv cc sw v bus v out bat ovsens clprog acpr sda prog irq gnd idgate t jmax = 125c, ja = 43c/w exposed pad (pin 21) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking package description temperature range LTC4099epdc#pbf LTC4099epdc#trpbf dqkt 20-lead (3mm 4mm) plastic utqfn C40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ LTC4099 3 4099f symbol parameter conditions min typ max units h clprog (note 4) ratio of measured v bus current to clprog program current 100ma mode 500ma mode 620ma mode 790ma mode 1a mode 1.2a mode low power suspend mode high power suspend mode 220 1200 1540 1980 2420 3080 10.9 65 ma/ma ma/ma ma/ma ma/ma ma/ma ma/ma ma/ma ma/ma i vout v out current available before discharging battery 100ma mode, bat = 3.3v 500ma mode, bat = 3.3v 620ma mode, bat = 3.3v 790ma mode, bat = 3.3v 1a mode, bat = 3.3v 1.2a mode, bat = 3.3v low power suspend mode high power suspend mode 0.23 1.6 135 672 840 1080 1251 1550 0.30 2.16 0.41 2.46 ma ma ma ma ma ma ma ma v clprog clprog servo voltage in current limit switching modes suspend modes 1.18 102 v mv v uvlo v bus undervoltage lockout rising threshold falling threshold 3.90 4.30 4.00 4.35 v v v duvlo v bus to bat differential undervoltage lockout v busCbat rising threshold v busCbat falling threshold 200 50 mv mv v out v out voltage switching modes, 0v < bat 4.2v, i vout = 0ma, battery charger off 3.5 bat + 0.3 4.7 v usb suspend modes, i vout = 250a 4.5 4.6 4.7 v f osc switching frequency 1.96 2.25 2.65 mhz r pmos pmos on-resistance 0.18 r nmos nmos on-resistance 0.30 i peak peak inductor current clamp 500ma to 1.2a input limit modes 3 a r susp suspend ldo output resistance 16 battery charger v float bat regulated output voltage 4.200v setting selected by i 2 c l 4.179 4.165 4.200 4.200 4.221 4.235 v v 4.100v default setting l 4.079 4.065 4.100 4.100 4.121 4.135 v v i chg_range constant-current mode charge current range i lim2/1/0 = 101, selectable by i 2 c 500-1200 ma i chg500ma zero scale battery charge current i lim2/1/0 = 101, i charge2/1/0 = 000 475 500 525 ma i chg1200ma full-scale battery charge current i lim2/1/0 = 101, i charge2/1/0 = 111 1140 1200 1260 ma i chg_step charge current i 2 c step size i lim2/1/0 = 101 100 ma i batq battery drain current v bus > v uvlo , powerpath switching regulator on, battery charger off, i vout = 0a 3.7 5 a v bus = 0v, i vout = 0a (ideal diode mode) 23 35 a v prog,trkl prog pin servo voltage in trickle charge bat < v trkl 0.100 v h prog ratio of i bat to prog pin current 1030 ma/ma electrical characteristics the l denotes the speci? cations which apply over the full operating temp- erature range, otherwise speci? cations are at t a = 25c. v bus = 5v, bat = 3.8v, dv cc = 3.3v, r prog = 1.02k, r clprog = 3.01k, unless otherwise noted. LTC4099 4 4099f symbol parameter conditions min typ max units v trkl trickle charge threshold voltage bat rising 2.7 2.85 3 v v trkl trickle charge hysteresis voltage 130 mv v rechrg recharge battery threshold voltage threshold voltage relative to v float C75 C100 C125 mv t term_range safety timer termination period range selectable by i 2 c, timer starts when bat = v float 1-8 hour t badbat bad battery termination time bat < v trkl 0.4 0.5 0.6 hour v c/x full capacity charge indication prog voltage (note 5) coverx1/0 = 00 90 100 110 mv coverx1/0 = 01 40 50 60 mv coverx1/0 = 10 190 200 210 mv coverx1/0 = 11 490 500 510 mv r on_chg battery charger power fet on-resistance (between v out and bat) i bat = 200ma 0.18 t lim junction temperature in constant- temperature mode selectable by i 2 c 85, 105 c bat-track external switching regulator control v wall absolute wall input threshold rising threshold falling threshold 4.15 4.3 3.2 4.45 v v v wall differential wall input threshold wallCbat rising threshold wallCbat falling threshold 0 90 37 50 mv mv v out regulation target under v c control 3.5 bat + 0.3 v i wallq wall quiescent current 130 a r acpr acpr pull-down strength 150 vh acpr acpr high voltage i acpr = 0ma v out v vl acpr acpr low voltage i acpr = 0ma 0 v overvoltage protection v ovcutoff overvoltage protection threshold rising threshold, r ovsens = 6.2k 6.10 6.35 6.70 v v ovgate ovgate output voltage input below v ovcutoff input above v ovcutoff 1.88 ? v ovsens 0 12 v v i ovsensq ovsens quiescent current v ovsens = 5v 40 a t rise ovgate time to reach regulation c ovgate = 1nf 2.5 ms overtemperature battery conditioner i discharge overtemperature battery discharge current only when enabled via i 2 c control 180 ma v allow maximum allowed overtemperature battery voltage only when enabled via i 2 c control 3.85 v ntc v too_cold cold temperature fault threshold voltage rising threshold hysteresis 72.3 73.8 3.6 75.3 %ntcbias %ntcbias v too_warm hot temperature fault threshold voltage falling threshold hysteresis 31.3 32.6 3.3 33.9 %ntcbias %ntcbias v overtemp critically high temperature fault threshold voltage falling threshold hysteresis 21.9 22.8 50 23.7 %ntcbias mv i ntc ntc leakage current ntc = ntcbias C50 50 na electrical characteristics the l denotes the speci? cations which apply over the full operating temp- erature range, otherwise speci? cations are at t a = 25c. v bus = 5v, bat = 3.8v, dv cc = 3.3v, r prog = 1.02k, r clprog = 3.01k, unless otherwise noted. LTC4099 5 4099f symbol parameter conditions min typ max units ideal diode v fwd forward voltage i vout = 10ma 15 mv r dropout internal diode on-resistance, dropout i vout = 200ma 0.18 i max diode current limit 2 a i 2 c port dv cc i 2 c logic reference 1.6 5.5 v i dvccq dv cc current scl/sda = 0khz 0.2 a v dvcc_uvlo dv cc uvlo 1v address i 2 c address 0001001 r w ? ? ? ? ? ? v irq irq pin output low voltage i irq = 5ma 65 100 mv i irq irq pin leakage current v irq = 5v 0 1 a v ih , sda, scl input high threshold 0.7 ? dv cc v v il , sda, scl input low threshold 0.3 ? dv cc v i ih , sda, scl input leakage high sda, scl = dv cc C1 1 a i il , sda, scl input leakage low sda, scl = 0v C1 1 a v ol digital output low (sda) i sda = 3ma 0.4 v f scl clock operating frequency 400 khz t buf bus free time between stop and start condition 1.3 s t hd_sda hold time after (repeated) start condi- tion 0.6 s t su_sda repeated start condition set-up time 0.6 s t su_sto stop condition time 0.6 s t hd_dat(out) data hold time 0 900 ns t hd_dat(in) input data hold time 0 ns t su_dat data set-up time 100 ns t low clock low period 1.3 s t high clock high period 0.6 s t sp spike suppression time 50 ns note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LTC4099 is guaranteed to meet performance speci? cations from 0c to 85c. speci? cations over the C 40c to 85c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 3: the LTC4099 includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the speci? ed maximum operating junction temperature may impair device reliability. note 4: total input current is the sum of quiescent current, i vbusq , and measured current given by: v clprog /r clprog ? (h clprog + 1) note 5: the prog pin always represents actual charge current. see the full capacity charge indication (c/x) section. electrical characteristics the l denotes the speci? cations which apply over the full operating temp- erature range, otherwise speci? cations are at t a = 25c. v bus = 5v, bat = 3.8v, dv cc = 3.3v, r prog = 1.02k, r clprog = 3.01k, unless otherwise noted. LTC4099 6 4099f output current (a) 0.01 40 efficiency (%) 50 60 70 80 100 0.1 1 4099 g05 90 500ma to 1.2a v bus input limit modes 100ma v bus input limit mode v clprog = 0v battery and v bus currents vs output current battery charging ef? ciency vs battery voltage with no external load (p bat /p vbus ) usb compliant output current available before discharging battery t a = 25c, v bus = 5v, bat = 3.8v, r prog = 1.02k, r clprog = 3.01k, unless otherwise noted. battery voltage (v) 2.7 50 efficiency (%) 70 90 3.0 3.3 3.9 3.6 60 80 100 4.2 4099 g06 500ma usb setting 100ma usb setting battery voltage (v) 2.7 0 output current (ma) 200 400 600 3.0 3.3 3.9 3.6 800 100 300 500 700 4.2 4099 g07 v bus input limit set for usb 500ma battery voltage (v) 2.7 0 output current (ma) 50 100 150 3.0 3.3 3.9 3.6 25 75 125 175 4.2 4099 g08 v bus input limit set for usb 100ma battery voltage (v) 2.7 0 charge current (v) 200 400 600 3.0 3.3 3.9 3.6 100 300 500 700 4.2 4099 g09 v float voltage set for 4.2v v bus input limit set for usb 500ma battery charger set for 1200ma usb limited battery charge current vs battery voltage battery and v bus currents vs output current output voltage vs output current usb compliant output current available before discharging battery powerpath switching regulator ef? ciency vs output current typical performance characteristics output current (ma) 0 current (ma) 400 600 800 4099 g01 200 0 C600 C200 C400 200 400 600 1000 battery current (charging) battery current (discharging) v bus input limit set for usb 500ma battery charger set for 800ma v bus current output current (ma) 0 current (ma) 400 600 800 800 4099 g02 200 0 C200 200 400 600 1000 battery current (charging) battery current (discharging) v bus input limit set for 790ma battery charger set for 500ma v bus current output current (ma) 0 output voltage (v) 4.0 4.5 5.0 800 4099 g03 3.5 3.0 200 400 600 1000 v bus input limit set for usb 500ma battery charger disabled bat = 4v bat = 3.4v battery voltage (v) 2.7 0 battery current (a) 10 20 3.0 3.3 3.9 3.6 5 15 25 4.2 4099 g04 i vout = 0a v bus = 0v v bus = 5v (suspend modes) battery drain current vs battery voltage LTC4099 7 4099f ideal diode v-i characteristics ideal diode resistance vs battery voltage forward voltage (v) 0 current (a) 0.6 0.8 1.0 0.16 4099 g11 0.4 0.2 0 0.04 0.08 0.12 0.20 internal ideal diode with supplemental external vishay si2333 pmos internal ideal diode only battery voltage (v) 2.7 resistance () 0.15 0.20 0.25 3.9 4099 g12 0.10 0.05 0 3.0 3.3 3.6 4.2 internal ideal diode with supplemental external vishay si2333 pmos internal ideal diode automatic low battery charge current reduction battery charge current vs temperature v bus current vs v bus voltage (suspend) v bus voltage (v) 1 v bus current (a) 30 40 50 5 4099 g18 20 10 0 2 3 4 6 i vout = 0ma battery voltage (v) 2.7 0 charge current (v) 40 20 60 80 100 120 140 3.0 3.3 3.6 3.9 4099 g10 4.2 v float voltage set for 4.2v v bus input limit set for usb 100ma usb limited battery charge current vs battery voltage typical performance characteristics t a = 25c, v bus = 5v, bat = 3.8v, r prog = 1.02k, r clprog = 3.01k, unless otherwise noted. low battery (instant-on) output voltage vs temperature temperature (c) C40 output voltage (v) 3.64 3.66 60 4099 g13 3.62 3.60 C15 10 35 85 3.68 bat = 2.7v i vout = 100ma v bus input limit set for usb 500ma normalized battery charger float voltage vs temperature temperature (c) C40 normalized float voltage 0.998 0.999 1.000 60 4099 g14 0.997 0.996 C15 10 35 85 1.001 oscillator frequency vs temperature temperature (c) C40 frequency (mhz) 2.25 2.30 2.35 60 4099 g17 2.20 2.15 2.10 C15 10 35 85 temperature (?c) C40 charge current (ma) 100 040 C20 20 60 80 120 4099 g16 105c setting 85c setting 0 100 200 300 400 500 600 thermal regulation v out (v) 3.50 0 charge current (ma) 100 200 300 400 500 3.55 3.60 3.65 4099 g15 3.70 LTC4099 8 4099f clprog voltage vs output current temperature (c) C40 2 quiescent current (ma) 5 8 11 14 17 20 C15 C10 35 60 4099 g20 85 i vout = 0a 500ma usb mode 100ma usb mode ovgate vs ovsens rising overvoltage threshold vs temperature temperature (c) C40 ovp threshold (v) 6.270 6.275 6.280 60 4099 g25 6.265 6.260 6.255 C15 10 35 85 input voltage (v) 0 0 ovgate (v) 2 4 6 8 10 12 24 68 4099 g27 ovsens connected to input through 6.2k resistor ovsens quiescent current vs temperature temperature (c) C40 quiescent current (a) 33 35 37 60 4099 g26 31 29 27 C15 10 35 85 v ovsens = 5v typical performance characteristics t a = 25c, v bus = 5v, bat = 3.8v, r prog = 1.02k, r clprog = 3.01k, unless otherwise noted. v bus quiescent current in suspend vs temperature temperature (c) C40 27 quiescent current (a) 30 33 36 39 42 45 C15 10 35 60 4099 g19 85 i vout = 0a v bus quiescent current vs temperature output voltage vs output current in suspend output current (ma) 0 output voltage (v) 4.0 4.5 5.0 2.0 4099 g21 3.5 3.0 2.5 0.5 1.0 1.5 2.5 suspend high suspend low bat = 3.3v v bus current vs output current in suspend output current (ma) 0 v bus current (ma) 1.5 2.0 2.5 2.0 4099 g22 1.0 0.5 0 0.5 1.0 1.5 2.5 suspend high suspend low bat = 3.3v output current (ma) 0 0 clprog voltage (v) 0.2 0.4 0.6 0.8 1.0 1.2 200 400 600 800 4099 g23 1000 v bus input limit set for usb 500ma battery charger disabled dv cc voltage (v) 1.5 0 dv cc current (a) 0.4 2.5 3.5 4.5 0.8 0.2 0.6 5.5 4099 g24 sda = scl = dv cc static dv cc current vs voltage LTC4099 9 4099f chrg pin voltage (v) 0 irq pin current (ma) 60 80 100 4 4099 g28 40 20 0 1 2 3 5 ovp disconnect waveform irq pin current vs voltage (pull-down state) i out 500a/div 0ma 500s/div 4099 g36 v out 20mv/div ac coupled suspend ldo transient response (500a to 1.5ma) typical performance characteristics t a = 25c, v bus = 5v, bat = 3.8v, r prog = 1.02k, r clprog = 3.01k, unless otherwise noted. v bus 5v/div ovgate 5v/div 500s/div 4099 g30 ovp input voltage 5v to 10v step 5v/div battery safety conditioner discharge current vs battery voltage battery charge current and voltage vs time output voltage vs battery voltage; battery charger overprogrammed ovp connection waveform input current vs temperature high voltage input charging ef? ciency vs battery voltage temperature (c) C40 0 input current (ma) 200 400 C15 10 60 35 100 300 500 85 4099 g31 500ma usb setting 100ma usb setting battery charger set for 1200ma battery voltage (v) 2.4 output voltage (v) 3.8 4.0 4.2 3.6 3.4 3.0 3.6 2.7 3.3 3.9 4.2 3.2 3.0 4.4 4099 g35 battery charger set for 1200ma 500ma usb setting 100ma usb setting battery voltage battery voltage (v) 3.6 battery current (ma) 60 90 120 30 3.8 4.0 3.7 3.9 4.1 4.2 0 150 4099 g32 battery conditioner enabled v ntc /v ntcbias < 0.219 v bus = 0v battery voltage (v) 3.0 efficiency (%) 80 60 40 3.6 3.3 3.9 4.2 20 0 100 4099 g33 conventional 5v buck without bat-track using the lt3653 with bat-track battery charge set for 700ma input voltage = 13.5v time (hours) 0 battery voltage (v) battery current (a) 4 7 3 2 2 4 1 3 56 8 1 5 0.8 0.6 0.4 0.2 00 1.0 4099 g34 v bus input limit set for 790ma battery charger set for 500ma float voltage set for 4.2v charger termination 4-hour setting 500ma ovgate 250s/div 4099 g29 0v 2v/div v bus LTC4099 10 4099f ovgate (pin 1): overvoltage protection gate output. connect ovgate to the gate pin of an external n-channel mosfet pass transistor. the source of the transistor should be connected to v bus and the drain should be connected to the products dc input connector. in the absence of an overvoltage condition, this pin is driven from an internal charge pump capable of creating suf? cient overdrive to fully enhance the pass transistor. if an overvoltage condition is detected, ovgate is brought rapidly to gnd to prevent damage to the LTC4099. ovgate works in conjunction with ovsens to provide this protection. ntc (pin 2): input to the negative temperature coef? cient thermistor monitoring circuit. the ntc pin connects to a negative temperature coef? cient thermistor which is typically copackaged with the battery to determine if the battery is too hot or too cold to charge. if the batterys temperature is out of range, charging is paused until the battery temperature re-enters the valid range. a low drift bias resistor is required from ntcbias to ntc and a thermistor is required from ntc to ground. ntcbias (pin 3): ntc thermistor bias output. connect a bias resistor between ntcbias and ntc, and a thermistor between ntc and gnd. v c (pin 4): bat-track auxiliary switching regulator control output. this pin drives the v c pin of an external linear technology step-down switching regulator. in conjunction with wall and acpr , it will regulate v out to maximize battery charger ef? ciency. wall (pin 5) : auxiliary power source sense input. wall is used to determine when power is available from an auxiliary power source. when power is detected, acpr is driven low and the usb input is automatically disabled. batsens (pin 6): battery voltage sense input. for proper operation, this pin must always be connected to bat. for best operation, connect batsens to bat physically close to the li-ion cell. prog (pin 7): charge current program and charge current monitor pin. connecting a resistor from prog to ground programs the charge current. if suf? cient input power is available in constant-current mode, this pin servos to one of eight possible i 2 c controllable voltages (see table 3). the voltage on this pin always represents the actual charge current by using the following formula: i v r bat prog prog = ? 1030 irq (pin 8): open-drain interrupt output. the irq pin can be used to generate an interrupt due to a multitude of maskable status change events within the LTC4099. see table 1. gnd (pin 9): ground. idgate (pin 10): ideal diode ampli? er output. this pin controls the gate of an external p-channel mosfet tran- sistor used to supplement the internal ideal diode. the source of the p-channel mosfet should be connected to v out and the drain should be connected to bat. bat (pin 11): single-cell li-ion battery pin. depending on available power and load, a li-ion battery on bat will either deliver system power to v out through the ideal diode or be charged from the battery charger. v out (pin 12): output voltage of the switching powerpath controller and input voltage of the battery charger. the majority of the portable product should be powered from v out . the LTC4099 will partition the available power be- tween the external load on v out and the internal battery charger. priority is given to the external load and any extra power is used to charge the battery. an ideal diode from bat to v out ensures that v out is powered even if the load exceeds the allotted power from v bus or if the v bus power source is removed. v out should be bypassed with a low impedance multilayer ceramic capacitor. v bus (pin 13): input voltage for the switching powerpath controller. v bus will usually be connected to the usb port of a computer or a dc output wall adapter. v bus should be bypassed with a low impedance multilayer ceramic capacitor. sw (pin 14): switching regulator power transmission pin. the sw pin delivers power from v bus to v out via the step-down switching regulator. an inductor should be con- nected from sw to v out . see the applications information section for a discussion of inductance value. pin functions LTC4099 11 4099f dv cc (pin 15): logic reference for the i 2 c serial port. a 0.01f bypass capacitor is required. scl (pin 16): clock input for the i 2 c serial port. the i 2 c input levels are scaled with respect to dv cc . sda (pin 17): data input/output for the i 2 c serial port. the i 2 c input levels are scaled with respect to dv cc . acpr (pin 18): auxiliary power source present output (active low). acpr indicates that the output of an external high voltage step-down switching regulator connected to wall is suitable for use by the LTC4099. acpr may be connected to the gate of an external p-channel mosfet transistor whose source is connected to v out and whose drain is connected to wall. acpr has a high level of v out and a low level of gnd. clprog (pin 19): usb current limit program and monitor pin. a 1% resistor from clprog to ground determines the upper limit of the current drawn from the v bus pin. a precise fraction of the input current, h clprog , is sent to the clprog pin when the high side switch is on. the switching regulator delivers power until the clprog pin reaches 1.18v. therefore, the current drawn from v bus will be limited to an amount given by h clprog and r clprog . there are a multitude of ratios for h clprog available by i 2 c control, two of which correspond to the 100ma and 500ma usb speci? cations (see table 2). a multilayer ceramic averaging capacitor is also required at clprog for ? ltering. ovsens (pin 20): overvoltage protection sense input. ovsens should be connected through a 6.2k resistor to the input power connector and the drain of an external n- channel mosfet pass transistor. when the voltage on this pin exceeds v ovcutoff , the ovgate pin will be pulled to gnd to disable the pass transistor and protect the LTC4099 from potentially damaging high voltage. exposed pad (pin 21): ground. the exposed pad and pin must be soldered to the pcb to provide a low electrical and thermal impedance connection to ground. pin functions LTC4099 12 4099f 15 2 + C + C + C + C + C + C + C too cold average input current limit controller too warm ntc ntcbias v out v prog v c/x c/x ntc t 19 clprog 13 v bus 1 ovgate 20 ovsens scl overtemperature 16 sda 17 dv cc i 2 c port interrupt logic 1.18v + C + + C average output voltage limit controller battery conditioner osc s 4.6v s 2 100mv 6v overvoltage protection suspend ldo i ldo /m i switch /n to usb or wall adpapter to automotive, firewire, etc. q r 3.6v 0.3v 4099 bd i bat /1030 + C + C prog 7 gnd 21 8 11 irq bat batsens single- cell li-ion optional external ideal diode pmos 10 idgate 12 v out to system load acpr constant-current constant-voltage battery charger + C 0v 15mv ideal diode + C bat + 0.3v 3.6v v out 4.3v + + C + C 14 sw 18 wall nonoverlap and drive logic gnd 9 + 5 v c 4 sw fb v in v c lt3480 bat-track hv control 6 3 +C + C 3.85v block diagram LTC4099 13 4099f timing diagram ack 123 write address r/ w 456789123456789123456789 00010 010 00010010 a7 a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 ack stop start sda scl ack sub address input data byte 4099 td01 ack 123 read address r/ w 456789123456789 00010 011 00010011 a7 a6 a5 a4 a3 a2 a1 a0 start sda scl ack output data byte 4099 td02 t su, dat t hd, sta t hd, dat sda scl t su, sta t hd, sta t su, sto 4099 td03 t buf t low t high start condition repeated start condition stop condition start condition t r t f t sp i 2 c read protocol i 2 c write protocol LTC4099 14 4099f introduction the LTC4099 is an i 2 c controlled power manager and li- ion charger designed to make optimal use of the power available from a variety of sources while minimizing power dissipation and easing thermal budgeting constraints. the innovative powerpath architecture ensures that the ap- plication is powered immediately after external voltage is applied, even with a completely dead battery, by prioritizing power to the application. the LTC4099 includes a bat-track monolithic step-down switching regulator for usb, wall adapters and other 5v sources. designed speci? cally for usb applications, the switching regulator incorporates a precision average in- put current limit for usb compatibility. because power is conserved, the LTC4099 allows the load current on v out to exceed the current drawn by the usb port making maximum use of the allowable usb power for battery charging. the switching regulator and battery charger communicate to ensure that the average input current never exceeds the usb speci? cations. for automotive and other high voltage applications, the LTC4099 provides bat-track control of an external linear technology step-down switching regulator to maximize bat- tery charger ef? ciency and minimize heat production. when power is available from both the usb and an aux- iliary input, the auxiliary input is prioritized. the LTC4099 contains both an internal 180m ideal diode as well as an ideal diode controller for use with an external p-channel mosfet. the ideal diodes from bat to v out guarantee that ample power is always available to v out even if there is insuf? cient or absent power at v bus or wall. the LTC4099 features an overvoltage protection circuit which is designed to work with an external n-channel mosfet to prevent damage to its input caused by ac- cidental application of high voltage. to prevent battery drain when a device is connected to a suspended usb port, an ldo from v bus to v out provides either a low power or high power usb suspend current to the application. finally, the LTC4099 has considerable adjustability built in so that power levels and status information can be controlled and monitored via a simple two wire i 2 c port. bat-track input current limited step-down switching regulator the power delivered from v bus to v out is controlled by a 2.25mhz constant-frequency step-down switching regu- lator. to meet the maximum usb load speci? cation, the switching regulator contains a measurement and control system which ensures that the average input current re- mains below the level programmed at the clprog pin and i 2 c port. v out drives the combination of the external load and the battery charger. if the combined load does not cause the switching power supply to reach the programmed input current limit, v out will track approximately 0.3v above the battery voltage. by keeping the voltage across the battery charger at this low level, power lost to the battery charger is minimized. figure 1 shows the power path components. if the combined external load plus battery charge current is large enough to cause the switching power supply to reach the programmed input current limit, the battery charger will reduce its charge current by precisely the amount necessary to enable the external load to be satis- ? ed. even if the battery charge current is programmed to exceed the allowable usb power, the usb speci? cation for average input current will not be violated; the battery charger will reduce its current as needed. furthermore, if the load current at v out exceeds the programmed power from v bus , the extra load current will be drawn from the battery via the ideal diodes even when the battery charger is enabled. the current out of clprog is a precise fraction of the v bus current. when a programming resistor and an av- eraging capacitor are connected from clprog to gnd, the voltage on clprog represents the average input current of the switching regulator. as the input current approaches the programmed limit, clprog reaches 1.18v and power delivered by the switching regulator is held constant. the input current limit has eight possible settings rang- ing from the usb suspend limit of 500a up to 1.2a for wall adapter applications. two of these settings are speci? cally intended for use in the 100ma and 500ma usb applications. operation LTC4099 15 4099f operation + C + + C 0.3v 1.18v 3.6v clprog i switch /n + C + C 15mv omv ideal diode pwm and gate drive average input current limit controller average output voltage limit controller constant-current constant-voltage battery charger + C 19 idgate 10 v out 12 sw 3.5v to (bat + 0.3v) to system load optional external ideal diode pmos single-cell li-ion 4099 f01 14 bat 11 batsens from usb or wall adapter 13 + 1 ovgate v bus ovsens to automotive, firewire, etc. acpr bat + 0.3v 3.6v v out 4.3v + + C + C 18 wall bat-track hv control 5 v c 4 sw fb hv in v c high voltage step-down switching regulator 6 s 2 6v overvoltage protection + C +C 20 when the switching regulator is activated, the average input current will be limited by the clprog programming resistor according to the following expression: ii v r h vbus vbusq clprog clprog clprog =+ + () ?1 where i vbusq is the quiescent current of the LTC4099, v clprog is the clprog servo voltage in current limit, r clprog is the value of the programming resistor and h clprog is the ratio of the measured current at v bus to the sample current delivered to clprog. refer to the electri- cal characteristics table for values of h clprog , v clprog and i vbusq . given worst-case circuit tolerances, the usb speci? cation for the average input current in 100ma or 500ma mode will not be violated, provided that r clprog is 3.01k or greater. see table 2 for other available settings of input current limit. while not in current limit, the switching regulators bat-track feature will set v out to approximately 300mv above the voltage at bat. however, if the voltage at bat is below 3.3v, and the load requirement does not cause the switching regulator to exceed its current limit, v out will regulate at a ? xed 3.6v, as shown in figure 2. this instant-on feature will allow a portable product to run im- mediately when power is applied without waiting for the figure 1. powerpath block diagram bat (v) 2.4 4.5 4.2 3.9 3.6 3.3 3.0 2.7 2.4 3.3 3.9 4099 f02 2.7 3.0 3.6 4.2 v out (v) no load 300mv figure 2. v out vs bat LTC4099 16 4099f battery to charge. if the load does exceed the current limit at v bus , v out will range between the no-load voltage and slightly below the battery voltage, indicated by the shaded region of figure 2. for very low battery voltages, the battery charger acts like a load and, due to the input current limit circuit, its current will tend to pull v out below the 3.6v instant-on voltage. to prevent v out from falling below this level, an undervoltage circuit automatically detects that v out is falling and reduces the battery charge current as needed. this reduction ensures that load current and voltage are always prioritized while allowing as much battery charge current as possible. see overprogramming the battery charger in the applications information section. the voltage regulation loop compensation is controlled by the capacitance on v out . an mlcc capacitor of 10f is required for loop stability. additional capacitance beyond this value will improve transient response. an internal undervoltage lockout circuit monitors v bus and keeps the switching regulator off until v bus rises above the rising v uvlo threshold (4.3v). if v bus falls below the falling v uvlo threshold (4v), system power at v out will be drawn from the battery via the ideal diodes. the volt- age at v bus must also be higher than the voltage at bat by v duvlo , or approximately 200mv, for the switching regulator to operate. bat-track auxiliary high voltage switching regulator control as shown in the block diagram, the wall, acpr and v c pins can be used in conjunction with an external high voltage linear technology step-down switching regula- tor, such as the lt3480 or lt3653, to minimize heat production when operating from higher voltage sources. bat-track control circuitry regulates the external switching regulators output voltage to the larger of bat+ 300mv or 3.6v in much the same way as the internal switching regulator. this maximizes battery charger ef? ciency while still allowing instant-on operation when the battery is deeply discharged. the feedback network of the high voltage regulator should be set to program an output voltage between 4.5v and 5.5v. when high voltage is applied to the external regulator, wall will rise toward this programmed output voltage. when wall exceeds approximately 4.3v, acpr is brought low, and the bat-track control of the LTC4099 overdrives the local v c control of the external high voltage step-down switching regulator. once the bat-track control is enabled, the output voltage is independent of the switching regula- tor feedback network. bat-track control provides a signi? cant ef? ciency advantage over the use of a simple 5v switching regulator output to drive the battery charger. with a 5v output driving v out , battery charger ef? ciency is approximately: ? total buck bat v v = ? 5 where buck is the ef? ciency of the high voltage switching regulator and 5v is the output voltage of the switching regulator. with a typical switching regulator ef? ciency of 87% and a typical battery voltage of 3.8v, the total battery charger ef? ciency is approximately 66%. assuming a 1a charge current, nearly 2w of power is dissipated just to charge the battery! with bat-track, battery charger ef? ciency is approxi- mately: ? total buck bat bat v vv = + ? . 03 with the same assumptions as above, the total battery charger ef? ciency is approximately 81%. this example works out to less than 1w of power dissipation, or almost 60% less heat. see the typical applications section for complete circuits using the lt3480 and lt3653 with bat-track control. ideal diode from bat to v out the LTC4099 has an internal ideal diode as well as a con- troller for an external ideal diode. both the internal and the external ideal diodes are always on and will respond quickly whenever v out drops below bat. if the load current increases beyond the power allowed from the switching regulator, additional power will be pulled from the battery via the ideal diodes. furthermore, if power to v bus (usb or wall adapter) is removed, then all of the operation LTC4099 17 4099f application power will be provided by the battery via the ideal diodes. the ideal diodes will be fast enough to keep v out from drooping with only the storage capacitance required for the switching regulator. the internal ideal diode consists of a precision ampli? er that activates a large on-chip mosfet transistor whenever the voltage at v out is approximately 15mv (v fwd ) below the voltage at bat. within the ampli? ers linear range, the small-signal resistance of the ideal diode will be quite low, keeping the forward drop near 15mv. at higher current levels, the mosfet will be in full conduction. precharge when a battery charge cycle begins, the battery charger ? rst determines if the battery is deeply discharged. if the battery voltage is below v trkl , typically 2.85v, an automatic trickle charge feature sets the battery charge current to one-? fth of the default charge current. if the low voltage persists for more than one-half hour, the battery charger automatically terminates and indicates via the i 2 c port that the battery was unresponsive. constant-current once the battery voltage is above v trkl , the charger begins charging in full power constant-current mode. the current delivered to the battery will try to reach v prog /r prog ? 1030 where v prog can be set by the i 2 c port and ranges from 500mv to 1.2v in 100mv steps. the default value of v prog is 500mv. depending on available input power and external load conditions, the battery charger may or may not be able to charge at the full programmed rate. the external load will always be prioritized over the battery charge current. likewise, the usb current limit program- ming will always be observed and only additional power will be available to charge the battery. when system loads are light, battery charge current will be maximized. as mentioned above, the upper limit of charge current is programmed by the combination of a resistor from prog to ground and the prog servo voltage value set in the i 2 c port. the charge current will be given by the following expression: i v r chg prog prog = ? 1030 eight values of v prog may be selected by the i charge2 , i charge1 and i charge0 bits in the i 2 c port. see table 3. in either the constant-current or constant-voltage charging modes, the voltage at the prog pin will be proportional to the actual charge current delivered to the battery. the charge current can be determined at any time by monitoring the prog pin voltage and using the following relationship: i v r bat prog prog = ? 1030 forward voltage (mv) (bat C v out ) 0 current (ma) 600 1800 2000 2200 120 240 300 4099 200 1400 1000 400 1600 0 1200 800 60 180 360 480 420 vishay si2333 external ideal diode LTC4099 ideal diode on semiconductor mbrm120lt3 figure 3. ideal diode v-i characteristics operation to supplement the internal ideal diode, an external p- channel mosfet transistor may be added from bat to v out . the idgate pin of the LTC4099 drives the gate of the external p-channel mosfet transistor for automatic ideal diode control. the source of the external p-channel mosfet should be connected to v out and the drain should be connected to bat. capable of driving a 1nf load, the idgate pin can control an external p-channel mosfet transistor having an on-resistance of 30m or lower. battery charger the LTC4099 includes a battery charger with low voltage precharge, constant-current/constant-voltage charging, c/x state-of-charge detection, automatic termination by safety timer, automatic recharge, bad cell detection and thermistor sensor input for out-of-temperature charge pausing. LTC4099 18 4099f recall, however, that in many cases the actual battery charge current, i bat , will be lower than the programmed current, i chg , due to limited input power available and prioritization of the system load drawn from v out . constant-voltage once the battery terminal voltage reaches the preset ? oat voltage, the battery charger will hold the voltage steady and the charge current will decrease naturally toward zero. two voltage settings, 4.100v and 4.200v, are avail- able for ? nal ? oat voltage selection via the i 2 c port. for applications that require as much run time as possible, the 4.200v setting can be selected. for applications that seek to extend battery life, the LTC4099s default setting of 4.100v should be used. full capacity charge indication (c/x) since the prog pin always represents the actual charge current ? owing, even in the constant-voltage phase of charging, the prog pin voltage represents the batterys state-of-charge during that phase. the LTC4099 has a full capacity charge indication comparator on the prog pin which reports its results via the i 2 c port. selection levels for the c/x comparator of 50mv, 100mv, 200mv and 500mv are available by i 2 c control. recall that the prog pin servo voltage can be programmed from 500mv to 1.2v. if the 1v servo setting represents the full charge rate of the battery (1c), then the 100mv c/x setting would be equivalent to c/10. likewise the 200mv c/x setting would represent c/5 and the 500mv setting c/2. charge termination the battery charger has a built-in termination safety timer. when the voltage on the battery reaches the user- programmed ? oat voltage of 4.100v or 4.200v, the safety timer is started. after the safety timer expires, charging of the battery will discontinue and no more current will be delivered. the safety timers default ending time of four hours may be altered from one to eight hours in one-hour increments by accessing the i 2 c port. automatic recharge after the battery charger terminates, it will remain off, drawing only microamperes of current from the battery. if the portable product remains in this state long enough, the battery will eventually self discharge. to ensure that the battery is always topped off, a new charge cycle will automatically begin when the battery voltage falls below v rechrg (typically 4.100v for the 4.200v ? oat voltage setting and 4.000v for the 4.100v ? oat voltage setting). in the event that the safety timer is running when the battery voltage falls below v rechrg , it will reset back to zero. to prevent brief excursions below v rechrg from resetting the safety timer, the battery voltage must be below v rechrg for more than 2.5ms. the charge cycle and safety timer will also restart if the v bus uvlo cycles low and then high (e.g., v bus or wall is removed and then replaced) or if the charger is momentarily disabled using the i 2 c port. the ? ow chart in figure 4 represents the battery chargers algorithm. thermistor measurement the battery temperature is measured by placing a nega- tive temperature coef? cient (ntc) thermistor close to the battery pack. the thermistor circuitry is shown in the block diagram. to use this feature, connect the thermistor between the ntc pin and ground and a bias resistor from ntcbias to ntc. the bias resistor should be a 1% resistor with a value equal to the value of the chosen thermistor at 25c (r25). the LTC4099 will pause charging when the resistance of the thermistor drops to 0.484 times the value of r25 or 4.84k for a 10k thermistor. for a vishay curve 2 thermis- tor, this corresponds to approximately 45c. if the battery charger is in constant-voltage (? oat) mode, the safety timer also pauses until the thermistor indicates a return to valid temperature. the LTC4099 is also designed to pause charging when the value of the thermistor increases to 2.816 times the value of r25. for a vishay curve 2 10k thermistor, this resistance, 28.16k, corresponds to approximately 0c. the hot and cold comparators each have approximately 3c of hysteresis to prevent oscillation about the trip point. if the curve 2 thermistors temperature rises above 60c, its value will drop to 0.2954 times r25. when this happens, the LTC4099 detects this critically high temperature and indicates it via the i 2 c port (see table 7). if this condition operation LTC4099 19 4099f occurs, it may be desirable to have application software enforce an emergency reduction of power in the portable product. it is possible to enable the battery conditioner circuit at this temperature to reduce stress caused by simultaneous high temperature and high voltage via the i 2 c port. see the overtemperature battery conditioner section. the thermistor detection circuit samples the thermistors value continuously whenever charging is enabled and periodically when it is not. when the charger is not en- abled, the thermistor is sampled for 150s approximately every 150ms. the thermistor data available to the i 2 c port is updated at the end of each sample period. clear event timer ntc out-of-range indicate ntc fault charge with constant-current pause event timer inhibit charging pause event timer charge with fixed voltage run event timer charge with 103v/r prog run event timer indicate charging power available timer > 30 minutes safety timer expired bat > 2.85v bat < v rechrg i bat < c/x no no yes yes yes yes yes yes no no bat > v float C e bat < 2.85v 2.85v < bat < v float C e no no no inhibit charging stop charging indicate battery fault bat rising through v rechrg bat falling through v rechrg indicate charging stopped indicate c/x reached 4099 f04 no yes yes battery state figure 4. battery charger flow chart operation LTC4099 20 4099f overtemperature battery conditioner since li-ion batteries deteriorate with full voltage and high temperature, the LTC4099 contains an automatic battery conditioner circuit that reduces the battery volt- age if both high temperature and high voltage are present simultaneously. recall that battery charging is inhibited if the thermistor temperature reaches 45c. if the thermistor temperature climbs above 60c, and the battery conditioner circuit is enabled, an internal load of approximately 180ma is ap- plied to bat. once the battery voltage drops to 3.9v, or the thermistor reading drops below 58c, the internal load is disabled. battery charging resumes once the thermistor temperature drops below 42c. when activated via the i 2 c port, the battery conditioner operates whether or not external power is available, charging has terminated or charging has been disabled by i 2 c control. note that this circuit can dissipate signi? cant power inside the LTC4099. to prevent an excessive temperature rise of the LTC4099, the LTC4099 reduces discharge current as needed to prevent a junction temperature rise above 120c. thermal regulation to prevent thermal damage to the LTC4099 or surrounding components during normal charging, an internal thermal feedback loop will automatically decrease the programmed charge current if the die temperature rises to 105c. this thermal regulation technique protects the LTC4099 from excessive temperature due to high power operation or high ambient thermal conditions, and allows the user to push the limits of the power handling capability with a given circuit board design. the bene? t of the LTC4099 thermal regulation loop is that charge current can be set according to actual, rather than worst-case, conditions for a given application with the assurance that the charger will auto- matically reduce the current in worst-case conditions. the thermal regulation set-point can be adjusted down to 85c from the default 105c setting using the i 2 c port, as explained in the input data section. overvoltage protection the LTC4099 can protect itself from the inadvertent ap- plication of excessive voltage to v bus or wall with just two external components: an n-channel mosfet and a 6.2k resistor. the maximum safe overvoltage magnitude will be determined by the choice of the external fet and its associated drain breakdown voltage. the overvoltage protection circuit consists of two pins. the ? rst, ovsens, is used to measure the externally applied voltage through an external resistor. the second, ovgate, is an output used to drive the gate pin of the external fet. when ovsens is below 6v, an internal charge pump will drive ovgate to approximately 1.88 ? ovsens. this will enhance the n-channel fet and provide a low impedance connection to v bus or wall which will, in turn, power the LTC4099. if ovsens should rise above 6v due to a fault or use of an incorrect wall adapter, ovgate will be pulled to gnd, disabling the external fet and, therefore, protecting the LTC4099. when the voltage drops below 6v again, the external fet will be re-enabled. see the applications information section for examples of multiple input protections, reverse input protection and recommended components. suspend ldo the LTC4099 provides a small amount of power to v out in suspend mode by including an ldo from v bus to v out . this ldo will prevent the battery from running down when the portable product has access to a suspended usb port. regulating at 4.6v, this ldo only becomes active when the internal switching converter is disabled. to remain compliant with the usb speci? cation, the input to the ldo is current-limited so that it will not exceed the low power or high power suspend speci? cation. if the load on v out exceeds the suspend current limit, the additional current will come from the battery via the ideal diodes. the sus- pend ldo sends a scaled copy of the v bus current to the clprog pin, which will servo to a maximum voltage of approximately 100mv. thus, the high power and low power suspend settings are related to the levels programmed by the same clprog resistor for the 100ma, 500ma and other switching power path settings. command bits, i lim2 operation LTC4099 21 4099f through i lim0 in the i 2 c port determine whether the sus- pend ldo will limit input current to the low power setting of 500a or the high power setting of 2.5ma. interrupt generation the irq pin on the LTC4099 is an open-drain output that can be used to generate an interrupt based on one or more of a multitude of maskable powerpath/battery charger change events. the interrupt mask register column in table 1 indicates the categories of events that can gener- ate an interrupt. if a 1 is written to a given location in the mask register, then any change in the status data of that category will cause an interrupt to occur. for example, if a 1 is written to bit 6 of the mask register, then an inter- rupt will be generated when the wall uvlo detects that either power has become available at wall, or that power was available and is no longer available from wall. if a 1 is written to bit 2 of the mask register, then an interrupt will be triggered by any change in the status bits of the battery charger, as given by table 8. likewise, a 1 at bit 3 will allow an interrupt due to any change in the thermistor status bits of table 7. the irq pin is cleared when the bus master acknowledges receipt of status data from a read operation. if the master does not acknowledge the status byte, the interrupt will not be cleared and the irq pin will not be released. upon generation of an interrupt, the current state of the LTC4099 is recorded in the i 2 c port for retrieval (see output data). i 2 c interface the LTC4099 may communicate with a bus master using the standard i 2 c 2-wire interface. the timing diagram shows the relationship of the signals on the bus. the two bus lines, sda and scl, must be high when the bus is not in use. external pull-up resistors or current sources, such as the ltc1694 smbus accelerator, are required on these lines. the LTC4099 is both a slave receiver and slave transmitter. the i 2 c control signals, sda and scl, are scaled internally to the dv cc supply. dv cc should be connected to the same power supply as the bus pull-up resistors. the i 2 c port has an undervoltage lockout on the dv cc pin. when dv cc is below approximately 1v, the i 2 c serial port is cleared, the LTC4099 is set to its default con? guration of all zeros and interrupts will be locked out. bus speed the i 2 c port is designed to be operated at speeds of up to 400khz. it has built-in timing delays to ensure correct operation when addressed from an i 2 c compliant master device. it also contains input ? lters designed to suppress glitches should the bus become corrupted. start and stop conditions a bus master signals the beginning of communications by transmitting a start condition. a start condition is generated by transitioning sda from high to low while scl is high. the master may transmit either the slave write or the slave read address. once data is written to the LTC4099, the master may transmit a stop condition which commands the LTC4099 to act upon its new command set. a stop condition is sent by the master by transitioning sda from low to high while scl is high. byte format each byte sent to, or received from, the LTC4099 must be eight bits long followed by an extra clock cycle for the acknowledge bit. the data should be sent to the LTC4099 most signi? cant bit (msb) ? rst. acknowledge the acknowledge signal is used for handshaking be- tween the master and the slave. when the LTC4099 is written to (write address), it acknowledges its write address as well as the subsequent two data bytes. when it is read from (read address), the LTC4099 acknowledges its read address only. the bus master should acknowledge receipt of information from the LTC4099. an acknowledge (active low) generated by the LTC4099 lets the master know that the latest byte of information was received. the acknowledge related clock pulse is generated by the master. the master releases the operation LTC4099 22 4099f sda line (high) during the acknowledge clock cycle. the LTC4099 pulls down the sda line during the write acknowledge clock pulse so that it is a stable low during the high period of this clock pulse. when the LTC4099 is read from, it releases the sda line so that the master may acknowledge receipt of the data. since the LTC4099 only transmits one byte of data, a master not acknowledging the data sent by the LTC4099 has no speci? c consequence on the operation of the i 2 c port. however, without a read acknowledge from the master, a pending interrupt from the LTC4099 will not be cleared and the irq pin will not be released. slave address the LTC4099 responds to a 7-bit address which has been factory programmed to 0b0001001[r/ w ]. the lsb of the address byte, known as the read/write bit, should be 0 when writing data to the LTC4099, and 1 when reading data from it. considering the address an 8-bit word, then the write address is 0x12, and the read address is 0x13. the LTC4099 will acknowledge both its read and write addresses. sub-addressed writing the LTC4099 has three command registers for control input. they are accessed by the i 2 c port via a sub- addressed writing system. each write cycle of the LTC4099 consists of exactly three bytes. the ? rst byte is always the LTC4099s write address. the second byte represents the LTC4099s sub address. the sub address is a pointer which directs the subsequent data byte within the LTC4099. the third bye consists of the data to be written to the location pointed to by the sub address. the LTC4099 contains control registers at only three sub address locations: 0x00, 0x01 and 0x02. only the two lsbs of the sub address byte are decoded, the remaining bits are dont-cares. therefore, a write to sub address 0x06 for example, is effectively a write to sub address 0x02. bus write operation the master initiates communication with the LTC4099 with a start condition and the LTC4099s write address. if the address matches that of the LTC4099, the LTC4099 returns an acknowledge. the master should then deliver the sub address. again, the LTC4099 acknowledges and the cycle is repeated for the data byte. the data byte is transferred to an internal holding latch upon the return of its acknowledge by the LTC4099. this procedure must be repeated for each sub address that requires new data. after one or more cycles of [address][sub-address][data], the master may terminate the communication with a stop condition. alternatively, a repeat start condition can be initiated by the master and another chip on the i 2 c bus can be addressed. this cycle can continue inde? nitely, and the LTC4099 will remember the last input of valid data that it received. once all chips on the bus have been addressed and sent valid data, a global stop can be sent and the LTC4099 will update its command latches with the data that it had received. bus read operation the bus master reads the status of the LTC4099 with a start condition followed by the LTC4099 read address. if the read address matches that of the LTC4099, the LTC4099 returns an acknowledge. following the acknowledgement of its read address, the LTC4099 returns one bit of status information for each of the next eight clock cycles. a stop command is not required for the bus read operation. input data table 1 illustrates the three data bytes that may be writ- ten to the LTC4099. the ? rst byte at sub address 0x00 controls the three input current limit bits i lim2 -i lim0 , the three battery charge current control bits i charge2 -i charge0 and the two c/x state-of-charge indication control bits coverx1 and coverx0. the input current limit settings are decoded according to table 2. this table indicates the maximum current that will be drawn from the v bus pin in the event that the load at v out (battery charger plus system load) exceeds the power available. any additional power will be drawn from the bat- tery. the default state for the input current limit setting is 000, representing the low power 100ma usb setting. operation LTC4099 23 4099f operation the battery charger current settings are decoded in table 3. the battery charger current settings are adjusted by selecting one of the eight servo voltages for the prog pin. recall that the programmed charge current is given by the expression: i v r chg prog prog = ? 1030 the default state for the battery charger current settings is 000, giving the lowest available servo voltage of 500mv. the coverx1 and coverx0 bits are decoded in table 4. the c/x setting controls the prog pin level that the LTC4099s c/x comparator uses to report full capacity charge. for example, if the 100mv setting is chosen, then the LTC4099 reports that its prog pin voltage has fallen below 100mv. for the 50mv setting, LTC4099 reports that its prog pin voltage has fallen below 50mv. the c/x settings are adjusted by comparing the prog pin voltage with the values shows in table 4. the default value for the c/x setting is 00, giving 100mv detection. the second byte of data at sub address 0x01 controls the three battery charger safety timer bits, timer2-timer0, the disable_charger bit, the enable_battery_ conditioner bit, the v float = 4.2v control bit and the t reg = 85c control bit. the timer2Ctimer0 bits control the duration of the bat- tery charger safety timer. the safety timer starts once the LTC4099 reaches the 4.100v or the 4.200v ? oat voltage. as long as input power is available, charging will con- tinue in ? oat voltage mode until the safety timer expires. table 5 lists the possible safety timer settings from 1 to 8 hours, and how to decode them. the default state for the LTC4099 safety timer is 4 hours. the disable_charger bit can be used to prevent battery charging if needed. this bit should be used with caution table 1. LTC4099 input data bytes sub address 0 sub address 1 sub address 2 command register 0 command register 1 irq mask register bit 7 i lim2 timer2 usbgood bit 6 i lim1 timer1 wallgood bit 5 i lim0 timer0 badcell bit 4 i charge2 disable_charger thermal_ reg bit 3 i charge1 enable_ battery_ conditioner thermistor_ status bit 2 i charge0 v float = 4.2v charger_status bit 1 coverx1 t reg = 85c not used bit 0 coverx0 not used not used table 2. i lim2 C i lim0 decode usb input current limit settings i lim2 i lim1 i lim0 i usb 0 0 0 100ma* 0 0 1 500ma 0 1 0 620ma 0 1 1 790ma 1 0 0 1000ma 1 0 1 1200ma 1 1 0 suspend low (500a) 1 1 1 suspend high (2.5ma) *default setting table 3. i charge2 C i charge0 decode battery charger current limit settings i charge2 i charge1 i charge0 v prog charge current r prog = 1.02k 0 0 0 500mv* 500ma 0 0 1 600mv 600ma 0 1 0 700mv 700ma 0 1 1 800mv 800ma 1 0 0 900mv 900ma 1 0 1 1000mv 1000ma 1 1 0 1100mv 1100ma 1 1 1 1200mv 1200ma *default setting table 4. c/x decode c/x indication settings coverx1 coverx0 v prog full capacity charge indication r prog = 1.02k 0 0 100mv* 100ma* 0 1 50mv 50ma 1 0 200mv 200ma 1 1 500mv 500ma *default setting LTC4099 24 4099f as it can prevent the battery charger from bringing up the battery voltage. without the ability to address the i 2 c port, only a low voltage on dv cc will clear the i 2 c port to its default state and re-enable charging. the enable_battery_conditioner bit enables the automatic battery load circuit in the event of simultaneously high battery voltage and temperature. see the overtem- perature battery conditioner section. the v float = 4.2v bit controls the ? nal ? oat voltage of the LTC4099s battery charger. a 1 in this bit position changes the charger from the default ? oat voltage value of 4.100v to the higher 4.200v level. the t reg = 85c control bit changes the LTC4099s battery charger junction thermal regulation temperature from its default value of 105c to a lower setting of 85c. this may be used to reduce heat in highly thermally compromised systems. in general, the high ef? ciency charging system of the LTC4099 will keep the junction temperature low enough to avoid junction thermal regulation. the third and ? nal byte of input data at sub address 0x02 is the mask register. the mask register determines which status change events or categories will be allowed to gener- ate an interrupt. a 1 written to a given position in the mask register allows status change in that category to generate an interrupt. a zero in a given position in the mask register prohibits the generation of an interrupt. the start-up state of the LTC4099 is all zeros for this register indicating that no interrupts will be generated without explicit request via the i 2 c port. see the interrupt generation section. output data one status byte may be read from the LTC4099. table 6 represents the status byte information. a 1 read back in any of the bit positions indicates that the condition is true. for example, 1s read back from bits 7 and 2 indicate that power is available at v bus , and that the battery chargers thermistor has halted charging due to an undertemperature condition at the battery. bit 7 in the status byte indicates the presence of power at v bus . criteria for determining this status bit is derived from the undervoltage lockout circuit on v bus and is given by the electrical parameters v uvlo and v duvlo . bit 6 indicates the presence of voltage available at the wall pin and is derived from the wall undervoltage lockout circuit. like the v bus pin, this pin has both an absolute voltage detection level given by the electrical parameter v wall , as well as a level relative to bat given by v wall . both of the conditions must be met for bit 6 to indicate the presence of power at wall. bit 5 indicates that the battery has been below the pre- charge threshold level of approximately 2.85v for more than one-half hour while the charger was attempting to charge. when this occurs, it is usually the result of a de- fective cell. however, in some cases a bad cell indication may be caused by system load prioritization over battery charging. system software can test for this by forcing a reduction of system load and restarting the battery charger via i 2 c (a disable followed by an enable). if the bad cell indication returns, then the cell is de? nitively bad. bit 4 indicates that the battery charger is in thermal regula- tion due to excessive LTC4099 junction temperature. recall that there are two i 2 c programmable junction temperature settings available at which to regulate, 85c and 105c. bit 4 indicates thermal regulation at whichever setting is chosen. bits 3 and 2 indicate the status of the thermistor measure- ment circuit and are decoded in table 7. the battery too cold and battery too hot states indicate that the thermistor temperature is out of range (either below 0c or above 45c for a curve 2 thermistor) and that charging has paused until a return to valid temperature. the battery overtemperature state indicates that the batterys thermistor has reached a critical temperature (above 60c for a curve 2 thermistor) and that long term battery capacity may be seriously compromised if the condition persists. bits 1 and 0 indicate the status of the battery charger, and are decoded into one of four possible battery charger states in table 8. the constant-current state indicates that the battery charger is attempting to charge with all available current up to the constant-current level programmed, and that the battery has not yet reached the ? oat voltage. the constant v, i bat > c/x bit indicates that the battery charger has entered the ? oat voltage phase of charging operation LTC4099 25 4099f (bat at 4.1v or 4.2v), but that the charge current is still above the c/x detection level programmed. the constant v, i bat LTC4099 26 4099f clprog resistor and capacitor as described in the bat-track input current limited step- down switching regulator section, the resistor on the clprog pin determines the average input current limit in each of the current limit modes. the input current will be comprised of two components, the current that is used to deliver power to v out , and the quiescent current of the switching regulator. to ensure that the usb speci? cation is strictly met, both components of input current should be considered. the electrical characteristics table gives the typical values for quiescent currents in all settings, as well as current limit programming accuracy. to get as close to the 500ma or 100ma speci? cations as possible, a precision resistor should be used. an averaging capacitor is required in parallel with the resistor so that the switching regulator can determine the average input current. this capacitor also provides the dominant pole for the feedback loop when current limit is reached. to ensure stability, the capacitor on clprog should be 0.1f or larger. choosing the inductor because the input voltage range and output voltage range of the power path switching regulator are both fairly nar- row, the LTC4099 was designed for a speci? c inductance value of 3.3h. some inductors which may be suitable for this application are listed in table 9. table 9. recommended inductors for the LTC4099 inductor type l (h) max i dc (a) max dcr ( ) size in mm (l w h) manufacturer lps4018 3.3 2.2 0.08 3.9 3.9 1.7 coilcraft www.coilcraft.com d53lc db318c 3.3 3.3 2.26 1.55 0.034 0.070 5 5 3 3.8 3.8 1.8 toko www.toko.com we-tpc type m1 3.3 1.95 0.065 4.8 4.8 1.8 wrth elektronik www.we-online.com cdrh6d12 cdrh6d38 3.3 3.3 2.2 3.5 0.063 0.020 6.7 6.7 1.5 7 7 4 sumida www.sumida.com applications information v bus and v out bypass capacitors the style and value of the capacitors used with the LTC4099 determine several important parameters such as regulator control loop stability and input voltage ripple. because the LTC4099 uses a step-down switching power supply from v bus to v out , its input current waveform contains high frequency components. it is strongly rec- ommended that a low equivalent series resistance (esr) multilayer ceramic capacitor be used to bypass v bus . tantalum and aluminum capacitors are not recommended because of their high esr. the value of the capacitor on v bus directly controls the amount of input ripple for a given load current. increasing the size of this capacitor will reduce the input ripple. the usb speci? cation allows a maximum of 10f to be connected directly across the usb power bus. if the overvoltage protection circuit is used to protect v bus , then its soft-starting nature can be exploited and a larger v bus capacitor can be used if desired. to prevent large v out voltage steps during transient load conditions, it is also recommended that a ceramic ca- pacitor be used to bypass v out . the output capacitor is used in the compensation of the switching regulator. at least 10f with low esr are required on v out . additional capacitance will improve load transient performance and stability. multilayer ceramic chip capacitors typically have excep- tional esr performance. mlccs combined with a tight board layout and an unbroken ground plane will yield very good performance and low emi emissions. there are several types of ceramic capacitors available , each having considerably different characteristics. for example, x7r ceramic capacitors have the best voltage and temperature stability. x5r ceramic capacitors have apparently higher packing density but poorer perfor- mance over their rated voltage and temperature ranges. y5v ceramic capacitors have the highest packing density, but must be used with caution because of their extreme LTC4099 27 4099f r1 c1 d1 v1 v2 d2 m1 m2 4099 f05 wall ovsens gnd ovgate LTC4099 v bus figure 5. dual overvoltage protection nonlinear characteristic of capacitance versus voltage. the actual in-circuit capacitance of a ceramic capacitor should be measured with a small ac signal and dc bias, as is expected in-circuit. many vendors specify the ca- pacitance versus voltage with a 1v rms ac test signal and, as a result, overstate the capacitance that the capacitor will present in the application. using similar operating conditions as the application, the user must measure or request from the vendor the actual capacitance to determine if the selected capacitor meets the minimum capacitance that the application requires. overprogramming the battery charger the usb high power speci? cation allows for up to 2.5w to be drawn from the usb port. the LTC4099s switching regulator regulates the voltage at v out to a level just above the voltage at bat while limiting power to less than the amount programmed at clprog. the charger should be programmed, with the prog pin, to deliver the maximum safe charging current without regard to the usb speci? cations. if there is insuf? cient current available to charge the battery at the programmed rate, the charger will reduce charge current until the system load on v out is satis? ed and the v bus current limit is satis? ed. programming the charger for more current than is available will not cause the average input cur- rent limit to be violated. it will merely allow the battery charger to make use of all available power to charge the battery as quickly as possible, and with minimal power dissipation within the charger. applications information overvoltage protection it is possible to protect both v bus and wall from overvoltage damage with several additional components as shown in figure 5. schottky diodes d1 and d2 pass the larger of v1 and v2 to r1 and ovsens. if either v1 or v2 exceeds 6v plus the schottky forward voltage, ovgate will be pulled to gnd and both the wall and usb inputs will be protected. each input is protected up to the drain-source breakdown, bv dss , of m1 and m2. in an overvoltage condition, the ovsens pin will be clamped at 6v. the external 6.2k resistor must be sized appropriately to dissipate the resultant power. for example, a 1/8w 6.2k resistor can have at most 1/8w 6.2k = 28v applied across its terminals. with the 6v at ovsens, the maximum overvoltage magnitude that this resistor can withstand is 34v. a 1/4w 6.2k resistor raises this value to 45v. ovsenss absolute maximum current rating of 10ma imposes an upper limit of 68v protection. table 10. recommended nmos fets for the overvoltage protection circuit nmos fet bv dss r on package fdn3725 30v 50m sot-23 si2302ads 20v 70m sot-23 ntljs4114 30v 40m 2mm 2mm dfn irlml2502 20v 35m sot-23 the charge pump output on ovgate has limited output drive capability. care must be taken to avoid leakage on this pin as it may adversely affect operation. LTC4099 28 4099f reverse-voltage protection the LTC4099 can also be easily protected against the application of reverse voltage, as shown in figure 6. d1 and r1 are necessary to limit the maximum v gs seen by mp1 during positive overvoltage events. d1s breakdown voltage must be safely below mp1s bv gs . the circuit shown in figure 6 offers forward voltage protection up to mn1s bv dss and reverse-voltage protection up to mp1s bv dss . ntc thermistors have temperature characteristics which are indicated on resistance-temperature conversion tables. the vishay-dale thermistor nths0603n02n1002-ff, used in the following examples, has a nominal value of 10k and follows the vishay curve 2 resistance-temperature characteristic. in the explanation below, the following notation is used. r25 = value of the thermistor at 25c r cold = value of thermistor at the cold trip point r hot = value of the thermistor at the hot trip point cold = ratio of r cold to r25 hot = ratio of r hot to r25 r nom = primary thermistor bias resistor (see figure 7) r1 = optional temperature range adjustment resistor (see figure 8) the trip points for the LTC4099s temperature quali? cation are internally programmed at 0.326 ? ntcbias for the hot threshold and 0.738 ? ntcbias for the cold threshold. therefore, the hot trip point is set when: r rr ntcbias ntcbias hot nom hot + = ?.? 0 326 and the cold trip point is set when: r rr ntcbias ntcbias cold nom cold + = ?.? 0 738 solving these equations for r cold and r hot results in the following: r hot = 0.4839 ? r nom and r cold = 2.816 ? r nom by setting r nom equal to r25, the above equations result in hot = 0.4839 and cold = 2.816. referencing these ratios to the vishay resistance-temperature curve 2 chart gives a hot trip point of about 45c and a cold trip point of about 0c. the difference between the hot and cold trip points is approximately 45c. r2 r1 usb/wall adapter 4099 f06 c1 d1 mn1 mp1 v bus positive protection up to bv dss of mn1 v bus negative protection up to bv dss of mp1 v bus ovsens ovgate LTC4099 figure 6. dual-polarity voltage protection alternate ntc thermistors and biasing the LTC4099 provides temperature-quali? ed charging if a grounded thermistor and a bias resistor are connected to ntc. by using a bias resistor whose value is equal to the room temperature resistance of the thermistor (r25), the upper and lower temperatures are preprogrammed to approximately 45c and 0c, respectively, when using a vishay curve 2 thermistor. the upper and lower temperature thresholds can be ad- justed by either a modi? cation of the bias resistor value or by adding a second adjustment resistor to the circuit. if only the bias resistor is adjusted, then either the upper or the lower threshold can be modi? ed, but not both. the other trip point will be determined by the characteristics of the thermistor. using the bias resistor, in addition to an adjustment resistor, both the upper and the lower tem- perature trip points can be independently programmed with the constraint that the difference between the upper and lower temperature thresholds must increase. exam- ples of each technique follow. applications information LTC4099 29 4099f C + C + r nom 10k r ntc 10k ntc 0.228 ? ntcbias overtemp 4099 f07 LTC4099 ntc block too_cold too_hot 0.738 ? ntcbias 0.326 ? ntcbias C + 2 ntcbias 3 t C + C + r nom 10.2k r ntc 10k r1 845 ntc 0.228 ? ntcbias overtemp 4099 f08 too_cold too_hot 0.738 ? ntcbias 0.326 ? ntcbias C + 2 LTC4099 ntc block t ntcbias 3 figure 7. standard ntc con? guration by using a bias resistor, r nom , different in value from r25, the hot and cold trip points can be moved in either direction. the temperature span will change somewhat due to the nonlinear behavior of the thermistor. the following equations can be used to easily calculate a new value for the bias resistor: rr rr nom hot nom cold = = 0 4839 25 2 816 25 . ? . ? where hot and cold are the resistance ratios at the desired hot and cold trip points. note that these equations are linked. therefore, only one of the two trip points can be chosen; the other is determined by the default ratios designed in the LTC4099. consider an example where a 50c hot trip point is desired. from the vishay curve 2 r-t characteristics, hot is 0.4086 at 50c. using the prior equation, r nom should be set to 8.45k. with this value of r nom , cold is 2.380 and the cold trip point is about 4c. notice that the span is now 46c rather than the previous 45c. this is due to the decrease in the temperature gain of the thermistor as the absolute temperature increases. the upper and lower temperature trip points can be in- dependently programmed by using an additional bias resistor as shown in figure 8. the following formulas can be used to compute the values of r nom and r1: rr rr nom cold hot nom hot = = ? . ? .? ? 2 332 25 1 0 4839 ? ?r25 for example, to set the trip points to 0c and 50c with a vishay curve 2 thermistor, choose: rkk nom == 2 816 0 4086 2 332 10 10 32 .?. . ?. the nearest 1% value is 10.2k: r1 = 0.4839 ? 10.2k C 0.4086 ? 10k = 0.850k the nearest 1% value is 845. the ? nal circuit is shown in figure 8, and results in an upper trip point of 50c and a lower trip point of 0c. figure 8. modi? ed ntc con? guration applications information LTC4099 30 4099f usb inrush limiting voltage overshoot on v bus may sometimes be observed when connecting the LTC4099 to a lab power supply. this overshoot is caused by long leads from the power supply to v bus . twisting the wires together from the supply to v bus can greatly reduce the parasitic inductance of these long leads, and keep the voltage at v bus to safe levels. usb cables are generally manufactured with the power leads in close proximity, and thus fairly low parasitic inductance. board layout considerations the exposed pad on the backside of the LTC4099 package must be securely soldered to the pc board ground. this is the primary ground pin in the package, and it serves as the return path for both the control circuitry and the synchronous recti? er. furthermore, due to its high frequency switching circuitry, it is imperative that the input capacitor, inductor, and output capacitor be as close to the LTC4099 as pos- sible, and that there be an unbroken ground plane under the LTC4099 and all of its external high frequency compo- nents. high frequency currents, such as the input current on the LTC4099, tend to ? nd their way on the ground plane along a mirror path directly beneath the incident path on the top of the board. if there are slits or cuts in the ground plane due to other traces on that layer, the current will be forced to go around the slits. if high frequency currents are not allowed to ? ow back through their natural least-area path, excessive voltage will build up and radiated emis- sions will occur (see figure 9). there should be a group of vias directly under the grounded backside leading directly down to an internal ground plane. to minimize parasitic inductance, the ground plane should be as close as pos- sible to the top plane of the pc board (layer 2). the idgate pin for the external ideal diode controller has extremely limited drive current. care must be taken to minimize leakage to adjacent pc board traces. 100na of leakage from this pin will introduce an additional offset to the ideal diode of approximately 10mv. to minimize leakage, the trace can be guarded on the pc board by surrounding it with v out connected metal, which should generally be less than 1v higher than idgate. battery charger stability considerations the LTC4099s battery charger contains both a constant- voltage and a constant-current control loop. the con- stant-voltage loop is stable without any compensation when a battery is connected with low impedance leads. excessive lead length, however, may add enough series inductance to require a bypass capacitor of at least 1f from bat to gnd. figure 9. higher frequency ground currents follow their incident path. slices in the ground plane cause high voltage and increased emissions 4099 f09 applications information LTC4099 31 4099f high value, low esr multilayer ceramic chip capacitors reduce the constant-voltage loop phase margin, possibly resulting in instability. ceramic capacitors up to 100f may be used in parallel with a battery, but larger ceramics should be decoupled with 0.2 to 1 of series resistance. furthermore, a 100f mlcc in series with a 0.3 resistor or a 100f os-con capacitor from bat to gnd is required to prevent oscillation when the battery is disconnected. in constant-current mode, the prog pin is in the feed- back loop rather than the battery voltage. because of the additional pole created by any prog pin capacitance, capacitance on this pin must be kept to a minimum. with no additional capacitance on the prog pin, the charger is stable for program resistor values as high as 25k. however, additional capacitance on this node reduces the maximum allowed program resistor. the pole frequency at the prog pin should be kept above 100khz. therefore, if the prog pin has a parasitic capacitance, c prog , the following equa- tion should be used to calculate the maximum resistance value for r prog : r khz c prog prog 1 2 100 ?? applications information high ef? ciency usb/automotive battery charger with overvoltage protection, reverse-voltage protection and low battery start-up v bus v out v c wall acpr automotive, firewire, etc. usb to c to c system load m4 c3 22f 0805 c1 4.7f 50v c5 22f 0805 c2 0.1f 10v c4 0.1f 0603 r5 100k 1 7 8 19 7 9, 21 6 9 3 418 14 12 10 11 6 5 4 13 d3 d1 d2 m3 r7 3.01k r8 1.02k r3 l2 3.3h l1 4.7h 4099 ta02 clprog prog LTC4099 lt3653 gnd sw batsens ovgate ovsens i 2 c irq ntcbias ntc 1 20 15-17 8 3 2 v out idgate bat li-ion 5 2 + r6 100k t r1 m1 m2 m1, m2, m4: si2333ds m3: ntljs4114n r4 6.2k v in gnd v c hvok i sense i lim sw boost 3 r2 27.4k typical applications LTC4099 32 4099f v bus ovgate wall acpr 5v wall adapter usb to c to c system load m6 c2 22f 0805 c1 2.2f 0603 c4 22f 0805 c3 0.1f 0603 r4 100k 19 7 9, 21 6 1 5 18 14 12 10 11 13 d4 d3 d2 d1 r6 3.01k r7 1.02k r2 m5 l1 3.3h 4099 ta03 clprog prog LTC4099 gnd sw batsens ovsense i 2 c irq ntcbias ntc 20 15-17 8 3 2 v out idgate bat li-ion + m3 m4 r5 100k t r1 m1 m2 r3 6.2k m1, m2, m5, m6: si2333ds m3, m4: ntljs4114n 3 usb/wall adapter battery charger with dual overvoltage protection, reverse-voltage protection and low battery start-up typical applications LTC4099 33 4099f v bus v c wall acpr automotive, firewire, etc. usb wall adapter to c to c system load m3 c5 22f 0805 c7 22f 0805 c1 4.7f 50v c2 68nf c4 22f c3 0.47f 50v c6 0.1f 0603 r6 100k r3 499k r1 150k 4 2 3 7 19 7 9, 21 6 9 4 5 18 14 12 10 11 11 1 6 8 5 10 13 m1 r8 3.01k r9 1.02k m2 d1 l2 3.3h l1 10h 4099 ta04 clprog prog LTC4099 lt3480 gnd sw batsens ovgate ovsens i 2 c irq ntcbias ntc 1 20 15-17 8 3 2 v out idgate bat li-ion + r7 100k t r2 40.2k r4 100k r5 6.2k r t v in run/ss pg gnd v c bd sync sw fb boost m1: ntljs4114n m2, m3: si2333ds 3 usb/automotive switching battery charger with 2a support from automotive input typical applications LTC4099 34 4099f low component count power manager with high and low voltage inputs v bus usb wall adapter to c to c system load m1 c5 22f 0805 c4 0.1f 0603 19 7 9, 21 6 14 12 10 11 13 r4 3.01k r2 100k r3 100k r5 1.02k l2 3.3h 4099 ta05 clprog prog LTC4099 gnd sw batsens i 2 c irq ntcbias ntc 1 20 15-17 8 3 2 v out idgate bat li-ion + c3 10f 0805 ovgate ovsens m1: si2333ds 3 v out v c wall acpr automotive, firewire, etc. c1 4.7f 50v c2 0.1f 10v 1 7 8 9 3 418 6 5 4 d1 l1 4.7h lt3653 5 2 v in gnd v c hvok i sense i lim sw boost r1 27.4k typical applications LTC4099 35 4099f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. pdc package 20-lead plastic utqfn (3mm 4mm) (reference ltc dwg # 05-08-1752 rev ?) 3.00 p 0.10 1.50 ref 4.00 p 0.10 note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 p 0.10 19 20 1 2 bottom viewexposed pad 2.50 ref 0.55 p 0.05 r = 0.115 typ pin 1 notch r = 0.20 or 0.25 s 45 o chamfer 0.25 p 0.05 0.50 bsc 0.127 ref 0.00 C 0.05 (pdc20) utqfn 0407 rev ? recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 p 0.05 0.25 p 0.05 2.50 ref 3.10 p 0.05 4.50 p 0.05 1.50 ref 2.10 p 0.05 3.50 p 0.05 package outline r = 0.05 typ 1.65 p 0.10 2.65 p 0.10 1.65 p 0.05 0.50 bsc 2.65 p 0.05 package description LTC4099 36 4099f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2008 lt 1108 ? printed in usa part number description comments ltc3555/ ltc3555-1/ ltc3555-3 switching usb power manager with li-ion/polymer charger, triple synchronous buck converter + ldo complete multifunction pmic: switchmode power manager and three buck regulators + ldo, charge current programmable up to 1.5a from wall adapter input, synchronous buck converters ef? ciency > 95%, adj outputs: 0.8v to 3.6v at 400ma/400ma/1a, bat-track adaptive output control, 200m ideal diode; 4mm 5mm qfn-28 package ltc3576/ ltc3576-1 switching power manager with usb on-the-go + triple step-down dc/dcs complete multifunction pmic: bidirectional switching power manager and three buck regulators + ldo, adj output down to 0.8v at 400ma/400ma/1a, overvoltage protection, usb on-the-go, charge current programmable up to 1.5a from wall adapter input, thermal regulation, i 2 c, high voltage bat-track buck interface, 180m ideal diode; 4mm 6mm qfn-38 package ltc4088 high ef? ciency usb power manager and battery charger maximizes available power from usb port, bat-track, instant-on operation, 1.5a maximum charge current, 180m ideal diode with <50m option, 3.3v/25ma always-on ldo, 3mm 4mm dfn package ltc4090/ ltc4090-5 high voltage usb power manager with ideal diode controller and high ef? ciency li-ion battery charger high ef? ciency 1.2a charger from 6v to 38v (60v max) input charges single-cell li-ion batteries directly from a usb port, thermal regulation; 200m ideal diode with <50m option, bat-track adaptive output control; ltc4090-5 has no bat-track, 3mm 6mm dfn-22 package. ltc4095 standalone usb li-ion/polymer battery charger 950ma charge current, timer termination + c/10 detection output 4.2v, 0.6% accurate float voltage, four chrg pin indicator states, 2mm 2mm dfn package ltc4098 high ef? ciency usb power manager and battery charger with regulated output voltage maximizes available power from usb port, bat-track, instant-on operation, 1.5a maximum charge current, 180m ideal diode with <50m option, automatic charge current reduction maintains 3.6v minimum v out , 3mm 4mm utqfn-20 package ltc4413 dual ideal diodes low loss replacement for oring diodes, 3mm 3mm dfn package thinsot is a trademark of linear technology corporation. typical application high ef? ciency usb/automotive battery charger with overvoltage protection and low battery start-up v bus v out v c wall acpr automotive, firewire, etc. usb to c to c system load m2 c3 22f 0805 c1 4.7f 50v c5 22f 0805 c2 0.1f 10v c4 0.1f 0603 r3 100k 1 7 8 19 7 9, 21 6 9 3 418 14 12 10 11 6 5 4 13 d2 m1 r5 3.01k r6 1.02k l2 3.3h l1 4.7h 4099 ta06 clprog prog LTC4099 lt3653 gnd sw batsens ovgate ovsens i 2 c irq ntcbias ntc 1 20 15-17 8 3 2 v out idgate bat li-ion 5 2 + r4 100k t m1: ntljs4114n m2: si2333ds r2 6.2k v in gnd v c hvok i sense i lim sw boost 3 r1 27.4k related parts |
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